(1) Field of the Invention
The invention relates to a process for making self-aligned gated field emitter devices which can be used for various applications including flat panel displays, electron sources for lithography and the like, memory writing devices, sensors and high speed switching devices.
(2) Description of the Related Art
Field emission devices have received increased attention in recent years, as integrated circuit manufacturing techniques have allowed for further miniaturization and new applications. Typically, one or many of a small, conical conductive emitter tip are formed on a conductive cathode. A second conductive surface, or gate, is formed in close proximity and parallel to the cathode surface, with the two surfaces separated by a dielectric layer. Apertures are formed in the gate layer and dielectric in the area of the emitter tips, with the gate opening surrounding the upper part of the emitter. When a positive bias is applied at the gate with respect to the cathode, electrons are emitted from the small emitter tip, with the current generated depending on the operating voltage, the sharpness of the tip and the emitter material work function.
One application for field emission devices is in the area of computer displays, where there is an increasing trend toward flat, thin, lightweight displays to replace the traditional cathode ray tube (CRT) device. One of several technologies that provide this capability is field emission displays (FED). An array of very small, conical emitters is manufactured, typically on a semiconductor substrate, and can be addressed via a matrix of columns and lines. These emitters are connected to a cathode, and surrounded by a gate. When the proper voltages are applied to the cathode and gate, electrons are emitted and attracted to the anode, on which there is cathodoluminescent material that emits light when excited by the emitted electrons, thus providing the display element. The anode is typically mounted in close proximity to the cathode/gate/emitter structure and the area in between is typically a vacuum.
There are several methods for fabricating the gated field emitters. One such process is taught in U.S. Pat. No. 4,857,161 by Borel et al. Another process uses a silicon oxide mask on a silicon wafer and the silicon is etched under the mask until a pointed silicon structure remains under the mask. Then the dielectric and conductor layer are deposited thereover and the "hat" removed. A third process forms the emitter tip first and then forms the dielectric and conductive layers thereover. An etchback is required to expose the emitter tip. This third method is shown for example in U.S. Pat. No. 5,186,670 to Doan et al. Other methods for fabricating gated field emitter include those shown in U.S. Pat. No. 5,151,061 to Sandhu and U.S. Pat. No. 5,188,977 to Stengl et al.
The FIGS. 1 through 4 illustrate how Borel et al fabricate their gated field emitter. Typically a silicon wafer 10 is used as the substrate. A dielectric layer 12, such as silicon oxide is formed over the wafer 10. A conducting coating 14 is formed over the dielectric layer 12. Thereafter, using lithography and etching techniques openings 15 are formed through the conducting layer 14 and dielectric layer 12 to the silicon wafer 10 to produce FIG. 1. A lift off layer 16, which could be composed of nickel, aluminum, aluminum oxide or the like is formed over the layer 14 at a low angle to prevent deposit within the hole 15 to produce FIG. 2. Molybdenum or the like is deposited under normal incidence to form emitters 18 within the openings and layer 20 on the surface of the lift off layer 18 as can be seen in FIG. 3. The gated field emitter is completed as seen in FIG. 4, with the lift off of the layer 20 by selectively dissolving the layer 16.
All of the above mentioned fabrication process for gated field emitters have serious drawbacks. The Borel et al process has several serious problems including (1) the lift off of the layer 20 by means of lift off layer 16 is difficult, (2) the reduction of the gate opening is limited and therefore operating voltages must be kept high, on the order of 80 to 100 volts, and (3) the formation of the lift off layer 16 requires a very low angle deposition to prevent any of the material from entering the openings 15. The "hat" method has many problems including (1) some of the "hats" fall off during etching causing reliability problems, (2) gate opening reduction is limited and therefore requires high operating voltages on the order of 80 to 100 volts and (3) only silicon and tantalum have been reported as material candidates for emitter. The third method of Doan et al has many problems which include (1) the gate cannot be made planar and (2) the device has a high capacitance and high leakage current, since in order to have the necessary gate opening the dielectric thickness must be minimized.
In "Fabrication of Self-aligned Gated Field Emitters", Journal of Micromechanical Microengineering, 2(1992), pp. 21-24, Liu et al describe a method for forming a conformal insulating layer over the emitter tip that provides a reduced gate opening. However, the emitter is exposed during the latter processing steps and thus subject to contamination. Emitter contamination can affect the work function of the emitter material in an irregular manner and result in severe fluctuation of emission. In U.S. Pat. No. 5,229,331, Doan et al also describe the use of a conformal insulating layer, however the gate-to-cathode insulating layer is formed of a flowable material and is planarized by a high-temperature reflow process.